The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the cell area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for the capacitor plates is conductively doped polysilicon. Such material is so utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying typography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors used for the deposition.
The prior art has recognized that capacitance of a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. Such roughness is typically transferred to the cell dielectric and overlying polysilicon layer interfaces, resulting in a larger surface area for the same planar area which is available for the capacitor. One procedure utilized to achieve surface roughening involves deposition under conditions which are intended to inherently induce a rough or rugged upper polysilicon surface. Such include low pressure chemical vapor deposition (LPCVD) techniques. Yet, such techniques are inherently unpredictable or inconsistent in the production of a rugged polysilicon film.
One type of polysilicon film which maximizes outer surface area is hemispherical grain polysilicon. Such can be deposited or grown by a number of techniques. One technique includes direct LPCVD formation at 590.degree. C. Another includes formation by first depositing an amorphous silicon film at 550.degree. C. using He diluted SiH.sub.4 (20%) gas at 1.0 Torr, followed by a subsequent high temperature transformation anneal. Hemispherical grain polysilicon is not, however, in situ doped during its deposition due to undesired reduction in grain size in the resultant film. Accordingly, methods must be utilized to conductively dope the hemispherical grain polysilicon after its deposition.
One such prior art technique and the drawbacks associated therewith is described with reference to FIG. 1. There illustrated is a wafer fragment 10 comprised of a bulk monocrystalline silicon substrate region 12 having a trench or capacitor container opening 14 provided therein. A thin layer 16 of in situ conductively doped polysilicon (not hemispherical grain) is provided over substrate 12 and within opening 14. Subsequently, a layer 18 of hemispherical grain polysilicon is deposited. During the course of subsequent wafer processing, inherent heating causes an anneal effect which drives conductivity enhancing dopant atoms from within layer 16 into layer 18 to render layer 18 electrically conductive. Alternately, a dedicated anneal step can be conducted.
The composite of layers 18 and 16 will ultimately be utilized as a lower capacitor storage plate in a finished capacitor construction. However even where layer 16 is excessively doped to accommodate for such out-diffusion, undesirable depletion effects develop in the resultant capacitor storage node, even after a dedicated anneal step. Such is exhibited or manifested as a drop in the net capacitance as the voltage is swept from zero volts in the negative direction.
One prior art alternate or additional technique for increasing dopant concentration in hemispherical grain layer 18 is by conducting angled ion implantation. Such is indicated by angled arrow pairs 20 and 22. Such represent separate ion implantation steps at opposing equal angles from vertical. Alternately instead of multiple different angled dopings, a constant angle can be utilized while the wafer is rotated. However, rotation during ion implantation can lead to considerable dopant non-uniformities and is typically less desirable than multiple angle implants. Regardless, the intent is to ion implant dopant atoms into layer 18 within trench 14. However, deep narrow contacts or trenches, such as illustrated trench 14, precludes adequate dopant implantation in the lower portions of the contact.
Accordingly, needs remain for providing improved capacitor constructions which minimizes or eliminates depletion effects, and which do not inherently require angled implanting.